PCI Express system and method of transitioning link state thereof

ABSTRACT

A PCI Express system and a method of transitioning link state thereof are provided. The PCI Express system has an upstream device, a downstream device and a link. The upstream device and the downstream device transmit data packets to both via the link, but when the link is in a first link state, data packet transmission is forbidden. In the beginning, the link is in a second link state and data packet transmission is normal. The upstream device transmits a data packet via the link to the downstream device. A time period is counted when receiving the data packet. The downstream device asserts an acknowledge packet to the upstream device to response the data pocket. After the timer is expired, the link is transited to the first link state.

This application claims the benefit of U.S. provisional application Ser.No. 60/683,313, filed May 23, 2005, and the benefit of Taiwanapplication Serial No. 95107634, filed Mar. 7, 2006, the subject mattersof which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to an apparatus and a method of transitioningstate, more specifically to an apparatus and a method of transitioninglink state for PCI Express.

2. Description of the Related Art

As the wheel of time moves on endlessly, the Peripheral DeviceInterconnect (PCI) mainly for the use of Personal Computers faces aproblem that the processors and input/output devices in the futuregeneration need higher transmission bandwidth. Such transmissionbandwidth gradually exceeds the working range of PCI. The industry thusdevelops a new generation PCI Express to be the standard regionalinput/output bus for all kinds of future processing platforms. The mostsignificant feature is the improvement of transmission efficiency.Single direction transmission rate can reach up to 2.5 GHz. Furthermore,the transmission rate can be increased by expanding the number of lanes.For example, using 4 lanes can speed up the transmission rate to 4times.

Advanced Configuration and Power Interface (ACPI) defines the devicestates (D-states) under every situation. And PCI Express further definesthe link states (L-states) between devices. Each link state has acorresponding relation to a device state.

Device state D0 (Full-On) represents that the device is under normaloperation. When the device is in the device state D0, the link betweendevices could be in the link states L0, L0 s, or L1.

Device states D1 and D2 are not specifically defined in APCI. Ingeneral, device state D2 is more power saving than device state D0 andD1 when the number of devices is few. Device state D1 is more powersaving than device state D2 when the number of devices is relativelarge. Device states D1 and D2 could be corresponding to the link stateL1.

Device state D3 (Off), including D3cold and D3hot states, represents theshut-down state. When the device is in D3cold state, the main power doesnot supply to the device. When the device is in D3hot state, the mainpower is supplied to the device. When the device is in D3cold state, thelink between the devices could be under the link state L2 if there hasan auxiliary power to supply power. If there is no auxiliary power, thelink could be under the link power state L3. Device state D3hotcorresponds to the link state L1.

Link state L0 is the state when the link between devices is in normaloperation. Link state L0 s can decrease the power consumption when thelink has short idle periods during data transmission.

When the link is in the link state L1, the devices are in pause statewith no request. This will decrease the demand of link power betweendevices. At the time there is no trigger of time pulse signal, and thePhase Lock Loop (PPL) will pause for any function.

Link state L2 and L3 are shut-down states. The difference between L2 andL3 is that the link state L2 is supplied by an auxiliary power, but thelink state L3 has no auxiliary power.

However, when the link is in a power saving link state, such as the linkstate L1, the link has to transit to a normal link state so that datapacket can be transmitted by the upstream device to the downstreamdevice. After the transmission ends, the link will transit back to powersaving link state L1. During the process, transmission error of datapacket easily causes the link states transitioning repeatedly. Moreseriously it may cause the system to shut down.

SUMMARY OF THE INVENTION

To address the above-detailed deficiencies, the present inventionprovides an apparatus of PCI Express system and a method oftransitioning link state thereof that avoids the transmission error ofdata packet.

The present invention provides a method of PCI Express transitioninglink state for a link between an upstream device and a downstreamdevice. The upstream device and the downstream device transmit data toboth through the link. Data transmission is forbidden when the link isin a first link state, and the downstream device is in the abnormaloperation state. The method includes: transiting the link to a secondlink state in which data packet transmission is normal. Then theupstream device transmits a data packet to the downstream device throughthe link. Later, a time period is counted when the downstream devicereceives the data packet. Then the downstream device asserts anacknowledge packet to the upstream device for responding the datapacket. When the time period is expired, and the downstream deviceasserts a power entry packet PM_Enter_L1 to the upstream device, and thelink is then transited back to the first link state.

The present invention also provides a PCI Express system including anupstream device, a downstream device, and a link. The downstream deviceis in a first device state. The upstream device and the downstreamdevice transmit data packets to both through the link. When the link isin a first link state, data transmission is forbidden. Thus the linktransits to a second link state to normally transmit data packets. Theupstream device transmits a data packet to the downstream device throughthe link. Then a time period is counted when the data packet isreceived, and the downstream device asserts an acknowledge packet to theupstream device for responding the data packet. When the time period isexpired, the downstream device asserts a power entry packet PM_Enter_L1to the upstream device, and the link is transited back to the first linkstate.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects, features, and advantages of the presentinvention will become better understood with regard to the followingdescription, and accompanying drawings where:

FIG. 1 is a schematic diagram of PCI Express link and layers.

FIG. 2 is a flowchart of the method of PCI Express transitioning linkstate

FIG. 3 is a relative waveform of the link transition between first linkstate and second link state.

DETAILED DESCRIPTION OF THE INVENTION

Referring to FIG. 1, a schematic diagram of PCIE system 100 is shown.The PCIE system 100 of the present invention includes an upstream device110, a downstream device 120, and a link 130 connected between theupstream device 110 and the downstream device 120.

The upstream device 110 includes: a Transaction Layer (TL) 111, a DataLink Layer (DLL) 112, and a Physical Layer (PHY) 113. And the downstreamdevice 120 also includes: a Transaction Layer 121, a Data Link Layer122, and a Physical Layer 123.

The upstream device can be, for example, a Root Complex (RC), and thedownstream device as well can be an End Point (EP).

The Transaction Layers 111 and 121 respectively generate data packets tothe Data Link Layers 112 and 122. The Transaction Layers 111 and 121also respectively receive data packets from the Data Link Layers 112 and122. Meanwhile the Transaction Layers 111 and 112 also manage the flowcontrol between devices. Data packets generated by or received from theTransaction Layers 111 and 121 are regarded as Transaction Layer Packets(TLPs).

The Data Link Layers 112 is in charge of data packets transmissionbetween the Physical Layers 113 and the Transaction Layer 111; similarlythe Data Link Layers 122 is in charge of data packets transmissionbetween the Physical Layers 123 and the Transaction Layer 121.

After receiving data packets, the Data Link Layers 112 and 122respectively transmit TLPs to the corresponding Transaction Layers 112and 121. The Data Link Layers 112 and 122 also respectively receive TLPsfrom the corresponding Transaction Layers 111 and 121, and thenrespectively output the data packets to the corresponding Physical Layer113 and 123. When the Data Link Layers 112 and 122 transmit the datapackets, error detection is performed for stably transmit the data packs

Data packets transmitted between the Data Link Layer 112 and thePhysical layer 113 are or between the Data Link Layer 122 and thePhysical layer 123 are regarded as Data Link Layer Packets (DLLPs).

The Physical Layers 113 and 123 are in charge of data packettransmission via the link 130 between the upstream devices 110 and thedownstream device 120.

The data packets from the downstream device 120 and received by PhysicalLayer 113 are transformed into DLLPs format and then transmitted to theData Link Layer 112. The DLLPs from the Data Link Layer 112 are receivedby the Physical layer 113 and then transmitted to the downstream device120 through the link 130. In the same manner, the data packets from theupstream device 110 and received by the Physical Layer 113 aretransformed DLLPs format and then transmitted to the Data Link Layer122. The DLLPs from the Data Link Layer 122 are received by the PhysicalLayer 123 and then transmitted to the upstream device 110 through thelink 130.

Referring to FIG. 2, a flowchart of PCI Express transitioning state isshown. The method is applied to the link 130 between the upstream device110 and the downstream device 120.

The present invention provides an apparatus and a method for transitinglink state and transmitting data when under abnormal working state. Thatis to say, the downstream device 120 is in a non-first device state (thefirst device state for example is D0 state). Assume the initial linkstate of the link 130 is in a first link state (ex. L1 state), datatransmission is forbidden.

The Data packets can not be transmitted through the link 130 in thefirst link state. As a result the link state of the link 130 has totransit to a second link state (ex. L0 state) so that data transmissioncan be normal (step 21). Later as shown in step 22, the upstream device110 asserts a data packet (ex. TLP) to the downstream device 120 throughthe link 130. The data packet is a command for changing or reading thedevice state of the downstream device 120. In step 23, a time period iscounted when the downstream device 220 receives the data packet. In step24, the downstream device 120 asserts an acknowledge packet to theupstream device 10 for responding the data packet. In step 25, when thetime period is expired, the downstream device 120 asserts a power entrypacket, PM_Enter_L1 (ex. DLLP), to the upstream device 110. In step 26,the upstream device 110 asserts a power request acknowledge packet,PM_Request_Ack, to the downstream device 120. In step 27, afterreceiving the PM_Request_Ack, the link 130 is transited to the firstlink state (ex. L0 state).

In step 23 to step 25, the time period could be: immediate time-out, (1CfgW+10 cycles), (32 QW TLP+1 CfgW+10 cycles), or (2*32 QW TLP+1 CfgW+10cycles).

Wherein, the CfgW is one data packet transmission period.

The CfgW is, for example a transmission period of a TLP transmitted fromthe Transaction Layer 111 of the upstream device 110 to the TransactionLayer 121 of the downstream device 120. 10 cycles represents a timeperiod for the downstream device to process a TLP. QW TLP represents theQW length of a TLP (ex: 1 QW TLP means that the TLP length is 1 QW, and1 QW is 8 bytes. Consequently 32 QW TLP is a TLP of 256 Bytes).

The time period counted to allow the acknowledge packet is receivedearlier than the power entry packet, PM_Enter_L1. This ensures that theacknowledge packet is received and the link 130 is later transited tothe first link state (ex. L1 state) by receiving the power entry packet,PM_Enter_L1.

FIG. 3 is the relative waveform of the link 130 transitioning betweenthe first link state (ex. L1 state) and the second link state (ex. L0state).

Assume that the initial state of the downstream device 120 is in thefirst device state (ex. D0 state), and the link state is in L0 state.After idle for a while, the downstream device 120 is transited to asecond device state (ex. D1 state), which is the non-first device state,at time point t1. At t1, the downstream device 120 also asserts a powerentry packet PM_Enter_L1 to the upstream device 110. At time point t2,the downstream device 220 receives the PM_Request_Ack and then the link130 is transited to the link state L1.

In the following paragraphs, the process described below is referred tothe flowchart in FIG. 2. After time point t2, the downstream device 120maintains in the second device state D1, the link 130 is in the linkstate L1 in which data packet transmission is forbidden.

If a data packet transmission is needed, the link 130 is transited fromlink state L1 to the link state L0 to allow data packet transmission. Attime point t3, the data packet is transmitted. When the downstreamdevice 120 receives the data packet, a time period ia counted and anacknowledge packet is asserted after processing the data packet. Laterat time point t4, when the time period is expired, the downstream device120 asserts a power entry packet PM_Enter_L1 data packet. At time pointt5, after the downstream device 120 receives a power request acknowledgepacket, PM_Request_Ack, the link 130 is transited to the link state L1.

The PCI Express system and method of transitioning link state thereofrevealed in the present invention has the advantage of transitioning thelink state from which data packet transmission is forbidden to which isallowed. And data transmission error during the transition of the linkstate can be avoided. Furthermore, the present invention avoids systemshut-down causing by repeated link state transitioning, and satisfiesthe power saving purpose of the prior art.

Although the present invention has been described in considerabledetail. Those skilled in the art should appreciate that they can readilyuse the disclosed conception and specific embodiments as a basis fordesigning or modifying other structures for carrying out the samepurposes of the present invention without departing from the spirit andscope of the invention as defined by the appended claims.

1. A method of transitioning link state, for a link connected between anupstream device and a downstream device, wherein an initial link stateof the link is in a first link state, and the downstream device is in anabnormal operation state, the method comprising: transitioning the linkstate from the first link state to a second link state; asserting a datapacket by the upstream device; counting a time period when thedownstream device receives the data packet; asserting an acknowledgepacket by the downstream device to the upstream device as a response tothe data packet; asserting a power entering packet by the downstreamdevice to the upstream device when the time period is expired; andasserting a power request acknowledge packet by the upstream device torespond to the power entering packet so as to transit the link from thesecond link state to the first link state.
 2. The method of claim 1wherein the data packet is a Transaction Layer Packet (TLP); the powerentering packet and the power request acknowledge packet arerespectively Data Link Layer Packets (DLLPs).
 3. The method of claim 1wherein the time period is not less than one data packet transmissionperiod plus 10 cycles.
 4. The method of claim 3 wherein the time periodfurther comprises 32 QW TLPs transmission period.
 5. The method of claim1 wherein the time period ensures the upstream device receives theacknowledge packet earlier than the power entering packet
 6. The methodof claim 1 wherein the first link state is the link state L0.
 7. Themethod of claim 1 wherein the second link state is the link state L1. 8.The method of claim 1 wherein the upstream device is a Root Complex andthe downstream device is an End Point.
 9. The method of claim 1 whereinthe method is applied to a PCI Express link.
 10. A data transmissionsystem comprising: an upstream device, for asserting a data packet; adownstream device, a time period is counted when the downstream devicereceives the data packet from the upstream device, at the same time, thedownstream device asserts an acknowledge packet to the upstream device;and a link, connected between the upstream device and the downstreamdevice for data transmission; wherein the downstream device asserts apower entering packet to the upstream device when the time period isexpired and the time period ensures the acknowledge packet is receivedearlier than power entering packet.
 11. The system of claim 10 whereinan initial link state of the link is at L1 state.
 12. The system ofclaim 11 wherein the link is transited to the link state L0 beforetransmitting the data packet.
 13. The system of claim 12 wherein theupstream device asserts a power request acknowledge packet to thedownstream device as a response to the power entering packet, and thelink is transited to L1 state.
 14. The system of claim 10 wherein theinitial link state of the downstream device is in an abnormal operationstate.
 15. The system of claim 10 wherein the data packet is utilized tochange or read the state of the downstream device.
 16. The system ofclaim 10 wherein the time period is not less than one data packettransmission period plus 10 cycles.
 17. The system of claim 16 whereinthe time period further comprises 32 QW TLPs transmission period. 18.The system of claim 10 wherein the data transmission system is a PCIExpress system.
 19. A method of link data transmission, for a linkconnected between an upstream device and a downstream device; wherein ainitial link state of the link is unable to transmit data packets; thedownstream device is in an abnormal operation state, the methodcomprising: asserting a data packet by the upstream device; counting atime period when the downstream device receives the data packet;asserting an acknowledge packet by the downstream device to the upstreamdevice as a response to the data packet; and asserting a power entrypacket by the downstream device to the upstream device when the timeperiod is expired; wherein the time period ensures the acknowledgepacket is received earlier than the power entry packet
 20. The method ofclaim 19 wherein the method further comprising: transiting the linkstate to a state able to transmit data packet.
 21. The method of claim20 wherein the method further comprising: asserting a power requestacknowledge packet responding to the power entering packet by theupstream device so as to transit the link state to a state unable totransmit data packet.
 22. The method of claim 19 wherein the time periodis not less than one data packet transmission period plus 10 cycles. 23.The method of claim 22 wherein the time period further comprises 32 QWTLPs transmission period.
 24. The method of claim 19 wherein the methodis applied to a PCI Express system.